No.
Date
No.
Date
No.
Date
Number system accounts for the code
Logical algebra: complete definite/no definite determination (Chinese,
Minimum degree: and-dragon expression s0p
(Jianeryi
Maximum source: component-component expression pOS
1Original meal list
The core software implementation of Logiyun Yuan
Small: Double plate type: TT
Ve
A0
A~FK
Yea
AE
5 doors
A∞H4
5 states 2
6≥
AKBo-k
1
One F
Voe
6-Yes
Tantitumen
OR gate
2.MOS type:
Voo
T9
Go
A
Vop
F
As
B--
5Speak
transmission gate
Ao
B--
or state
lacquer door
wxya
My nimen-
No.
Date
No
Date
4. However, the analysis of combined thermoelastic circuit accounts for the design.
1.Analysis
①D coding operation and priority coder
1Five-exclusion theory input coder: 2 ~
2 priority bias coder: 2-person. There is no fixed number of times if the number is endless.
3 Medium-sized Dou Cheng Priority Encoder: 74148
Expansion of customer volume: 18-3)*2=064)
② Decoder
》Zhongxiang Benmo Integrated Zecoder: 20137.5s) Zangma Capacity Exhibition: The front-end output is used for post-account selection
32-digit star coder, unique truth table, simplification to obtain the most identical expression
②Multiplexers and splitters
1) Multiplexer: Use address code selection as the source!
2) Zhongshi spicy yellow integrated multi-channel remote selection tired: 74153
Capacity expansion: hierarchical selection.
•
32 splitter
Select the data sink based on the person's address code.
④ Numerical comparison device
21. The ratio of binary numbers: (A>B)=AB, UACB:AB, 4A-B2-original mother?
2) 2-digit binary numbers: can be composed of 1-digit binary numbers and other combinations
3) Medium-scale integrated digital wine reporting device: 7485
⑤ Adder and subtractor
1 Food adder: A..Bw, Chr=Sh.Cr
》Bitwise carry adder: carry special transfer
3) Carry lookahead adder:
Sa-Patcnd
Gn~An'B.
4) Medium vision module integrated adder: 74283
Capacity expansion: forwarding of letters and so on.
58421BCD code adding circuit: For numbers whose sum is greater than 9, a correction of adding 6 is required.
2
Entering a steady state: At the same time, Li made mistakes like this
Primary transformation: bubble-free input changes. Output (meaning once
Empty season and confirmed output change multiple times when CP=1
No.
Date
Set juice
The direct value representation of individual and symmetrical expressions eliminates the graph.
Competition and adventure: transitional
① Algebraic sliding elimination: Add redundant additions to eliminate possible A18 or A100 forms.
◎Cajon graph elimination: add a few extra features and connect all adjacent minimum terms.
- Shi Hou's circuit series / analysis of Zhan Mo Jue
analysis
①Latch core and original device
) Rice saving point: There is no e in this hair style
Gated RS register, Western secret state, one-time transformation, honey transfer
E-
P latch: somersault.
S'-
2) Hemp hair device, pulse vaginal hair style, printed hair
Master-slave type:
Master type A-S hair carving device: metastable state, one change QT'=S'+Q"R (C.S-o)
Make your hair water-friendly: - changes
Mainly type port trigger=v
Hairstyle with worms on the edge:~
②Register: 1 original limiter 1bit.; Acceptance: 5CP Yuanguan: Return to bag: related to eP.
③Counter:
74161: Asynchronous clearing and synchronous sending.
Capacity expansion: Carry is very easy to enable leakage.
20160:1 Sishang, decimal,
Capacity expansion: Same as above
④Shift register, store wine, serial one and seal replacement, and one word replacement.
Capacity expansion: serial and serial
Westward migration storage type juice counter: "ring punishment juice counter: M public frequency
Twisted ring counter: 2M frequency division.
Signal generator: return property or transducer (specific process)
On the contrary, if pigs are passed and they are combined with XOR, then three doses will be produced.
->ut
Feedback logic F=98-0d
No.
Date
(Synchronization: Wuyinhu adventure; periodic large consumption
No.
Date.
Kaixi: glitches, adventures in competition; not without a plan
(Finite State Machine: Finite StateMachine)
e9-Synchronization timing ratio analysis
{Menly type,
Input, status-output
Moore type: status output
The beauty of the tactile organ - the shape equation of the two hair organs, losing 3, the shape forgetting the table, benefiting Zhou,
The number of transmitters is the hall status number.
The shape of kudzu moves in the same direction
state diagram
Function
2. (Yue Si Jin Sequential Circuit) Design
① Draw the original state diagram and original state table.
②Status simplification
1) The state simplification of the sequential circuit of perfect gold contemplation.
》Incomplete timing ratio status 1 tube
Contains a table - a correlation ratio - a maximum capacity class - a minimum status storage table
③ Status distribution: phase order and prison rules.
1) Alternating the two cash sets of the next state
2) Two states of the next present state with different inputs,
32 outputs the two reporting states of the phase division.
④ Original type: output function; return FM like this
⑤ Add a power-on reset circuit or additional circuit if necessary to make the F5M self-start.
3. Qingxu and Yuanxuan: essential nature.
① Add Xiaochong absolute device to prevent time deviation.
① Time coordination of signals
③ Use bottom circuit to reliably combine reset and set signals.
④ There are many reliable clocks.
21③
②y
②
No.
Date
K. Memory and programmable selectable devices.
1 Summer has me, Jin Yan also
Tight storage: selective extraction based on address code.
1-RAM:randem aceess memny
Save nothing
address
2棣知1
① SPAM:
Do not brush the system
, small capacity, large power
②DRAM:
Needs to be refreshed, large capacity, small power consumption.
Capacity expansion:
6-digit extension: one address road 1/year Zhongyuan Jing
②Word expansion: multi-address code-20.
③Expansion of guest accommodation~
2.ROM:reael anly meary
0PROM: primary partial column; burst wire
②EPROM: Multiple leaks, UV ceramic bit.
② EYPROM: multiple graining: tunnel effect
④flosh memerily
3.PLD: prregremabl logfs device
①SPLD:
It becomes hum (harmonic) with Mo Ta Address).
PAL,GAL
V
×
P2A
V
V
RDM
×
V
② CPLD: multiple GALs.
③FPGA: Multiple CLB
27 words xM bits.